1. Field
Exemplary embodiments of the present invention relate generally to semiconductor designing technology and, more particularly, to an address generation circuit for generating a redundancy address, and a semiconductor memory device including the address generation circuit.
2. Description of the Related Art
Semiconductor memory devices are largely divided into volatile memory devices and non-volatile memory devices.
Volatile memory devices are quick at writing and reading data, but the volatile memory devices lose the data stored therein when power supply is cut off. On the other hand, non-volatile memory devices are relatively slow at writing and reading data but they retain the data stored therein even though power supply is cut off. For this reason, the non-volatile memory devices are used to store data if the data have to be retained regardless of the power supply. Non-limiting examples of the non-volatile memory devices include a Read Only Memory (ROM), a Mask ROM (MROM), a Programmable ROM (PROM), an Erasable Programmable ROM (EPROM), an Electrically Erasable Programmable ROM (EEPROM), a flash memory, a Phase-Change Random Access Memory (PRAM), a Magnetic RAM (MRAM), a Resistive RAM (RRAM), a Ferroelectric RAM (FRAM) and the like. A flash memory may be NOR-type or NAND-type flash memory.
A flash memory has the advantage of a RAM device that data may be freely programmed or erased and the advantage of a ROM device that the data stored in the flash memory are retained even though power supply is cut off. Flash memory is widely used as storage media for portable electronic devices, such as digital cameras, Personal Digital Assistants (PDA), MP3 players, and the like.
A column address repair operation for replacing a failure memory cell with a normal memory cell may be performed to complement failure of a memory cell, which may occur in the process of fabricating a semiconductor memory device. As a result, the column address control time may be delayed due to the column address repair operation when a data input operation or a data output operation is performed in the semiconductor memory device. The delay in the column address repair operation may lead to timing delay in the entire data input/output operation that is performed in the inside of the semiconductor memory device. To internally complement the timing between data and clocks for the time delay according to the column address control time, additional delay cells are used in the semiconductor memory device. However, as the semiconductor memory device operates at a high data rate, use of delay cells may be increased substantially, which may lead to increased current consumption and chip size and fluctuation in process, voltage and temperature (PVT) conditions.